1. Field of the Invention
The present invention relates to a thin film magnetic memory device. More particularly, the present invention relates to a random access memory (RAM) including memory cells having a magnetic tunnel junction (MTJ).
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device is a memory device that stores data in a non-volatile manner using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit and is capable of random access to each thin film magnetic element.
In particular, recent announcement shows that significant progress in performance of the MRAM device is achieved by using thin film magnetic elements having a magnetic tunnel junction (MTJ) as memory cells. The MRAM device including memory cells having a magnetic tunnel junction is disclosed in technical documents such as “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, February 2000, and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 83 is a schematic diagram showing the structure of a memory cell having a magnetic tunnel junction (hereinafter, also simply referred to as “MTJ memory cell”).
Referring to FIG. 83, the MTJ memory cell includes a magnetic tunnel junction MTJ whose resistance value varies according to the storage data level, and an access transistor ATR. The access transistor ATR is formed from a field effect transistor, and is coupled between the magnetic tunnel junction MTJ and the ground voltage Vss.
For the MTJ memory cell are provided a write word line WWL for instructing a data write operation, a read word line, RWL for instructing a data read operation, and a bit line BL serving as a data line for transmitting an electric signal corresponding to the storage data level in the data read and write operations.
FIG. 84 is a conceptual diagram illustrating the data read operation from the MTJ memory cell.
Referring to FIG. 84, the magnetic tunnel junction MTJ has a magnetic layer FL having a fixed magnetic field of a fixed direction (hereinafter, also simply referred to as “fixed magnetic layer FL”), and a magnetic layer VL having a free magnetic field (hereinafter, also simply referred to as “free magnetic layer VL”). A tunnel barrier TB formed from an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. According to the storage data level, either a magnetic field of the same direction as that of the fixed magnetic layer FL or a magnetic field of the direction different from that of the fixed magnetic layer FL has been written to the free magnetic layer VL in a non-volatile manner.
In reading the data, the access transistor ATR is turned ON in response to activation of the read word line RWL. As a result, a sense current Is flows through a current path formed by the bit line BL, magnetic tunnel junction MTJ, access transistor ATR and ground voltage Vss. The sense current Is is supplied as a constant current from a not-shown control circuit.
The resistance value of the magnetic tunnel junction MTJ varies according to the relative relation of the magnetic field direction between the fixed magnetic layer FL and the free magnetic layer VL. More specifically, in the case where the fixed magnetic layer FL and the free magnetic layer VL have the same magnetic field direction, the magnetic tunnel junction MTJ has a smaller resistance value as compared to the case where both magnetic layers have different magnetic field directions.
Accordingly, in the data read operation, a voltage change produced at the magnetic tunnel junction MTJ due to the sense current Is varies according to the magnetic field direction stored in the free magnetic layer VL. Thus, by starting supply of the sense current Is with the bit line BL precharged to a high voltage, the storage data level in the MTJ memory cell can be read by monitoring a voltage level change on the bit line BL.
FIG. 85 is a conceptual diagram illustrating the data write operation to the MTJ memory cell.
Referring to FIG. 85, in the data write operation, the read word line RWL is inactivated, and the access transistor ATR is turned OFF. In this state, a data write current for writing a magnetic field to the free magnetic layer VL is applied to the write word line WWL and the bit line BL. The magnetic field direction of the free magnetic layer VL is determined by combination of the respective directions of the data write current flowing through the write word line WWL and the bit line BL.
FIG. 86 is a conceptual diagram illustrating the relation between the respective directions of the data write current and the magnetic field in the data write operation.
Referring to FIG. 86, a magnetic field Hx of the abscissa indicates the direction of a magnetic field H(WWL) produced by the data write current flowing through the write word line WWL. A magnetic field Hy of the ordinate indicates the direction of a magnetic field H(BL) produced by the data write current flowing through the bit line BL.
The magnetic field direction stored in the free magnetic layer VL is updated only when the sum of the magnetic fields H(WWL) and H(BL) reaches the region outside the asteroid characteristic line shown in the figure. In other words, the magnetic field direction stored in the free magnetic layer VL is not updated when a magnetic field corresponding to the region inside the asteroid characteristic line is applied.
Accordingly, in order to update the storage data of the magnetic tunnel junction MTJ by the data write operation, a current must be applied to both the write word line WWL and the bit line BL. Once the magnetic field direction, i.e., the storage data, is stored in the magnetic tunnel junction MTJ, it is held therein in a non-volatile manner until a new data write operation is conducted.
The sense current Is flows through the bit line BL in the data read operation. However, the sense current Is is generally set to a value that is smaller than the above-mentioned data write current by about one or two orders of magnitude. Therefore, it is less likely that the storage data in the MTJ memory cell is erroneously rewritten during the data read operation due to the sense current Is.
The above-mentioned technical documents disclose a technology of forming an MRAM device, a random access memory, having such MTJ memory cells integrated on a semiconductor substrate.
FIG. 87 is a conceptual diagram showing the MTJ memory cells arranged in rows and columns in an integrated manner.
Referring to FIG. 87, with the MTJ memory cells arranged in rows and columns on the semiconductor substrate, a highly integrated MRAM device can be realized. FIG. 87 shows the MTJ memory cells arranged in n rows by m columns (where n, m is a natural number).
As described before, the bit line BL, write word line WWL and read word line RWL must be provided for each MTJ memory cell. Accordingly, n write word lines WWL1 to WWLn, n read word lines RWL1 to RWLn, and m bit lines BL1 to BLm are required for the n×m MTJ memory cells.
Thus, the MTJ memory cells are generally provided with the independent word lines for the read and write operations.
FIG. 88 is a structural diagram of the MTJ memory cell provided on the semiconductor substrate.
Referring to FIG. 88, the access transistor ATR is formed in a p-type region PAR of the semiconductor main substrate SUB. The access transistor ATR has source/drain regions (n-type regions) 110, 120 and a gate 130. The source/drain region 110 is coupled to the ground voltage Vss through a metal wiring formed in a first metal wiring layer M1. A metal wiring formed in a second metal wiring layer M2 is used as the write word line WWL. The bit line BL is provided in a third metal wiring layer M3.
The magnetic tunnel junction MTJ is provided between the second metal wiring layer M2 of the write word line WWL and the third metal wiring layer M3 of the bit line BL. The source/drain region 120 of the access transistor ATR is electrically coupled to the magnetic tunnel junction MTJ through a metal film 150 formed in a contact hole, the first and second metal wiring layers M1 and M2, and a barrier metal 140. The barrier metal 140 is a buffer material for providing electrical coupling between the magnetic tunnel junction MTJ and the metal wirings.
As described before, the MTJ memory cell is provided with the read word line RWL independently of the write word line WWL. In addition, in the data write operation, a data write current for generating a magnetic field equal to or higher than a predetermined value must be applied to the write word line WWL and the bit line BL. Accordingly, the bit line BL and the write word line WWL are each formed from a metal wiring.
On the other hand, the read word line RWL is provided in order to control the gate voltage of the access transistor ATR, and a current need not be actively applied to the read word line RWL. Accordingly, from the standpoint of the improved integration degree, the read word line RWL is conventionally formed from a polysilicon layer, polycide structure, or the like in the same wiring layer as that of the gate 130 without providing an additional independent metal wiring layer.
As described in connection with FIG. 84, the data read operation of the MTJ memory cell is conducted based on the voltage change caused by the sense current (Is in FIG. 84) supplied to the magnetic tunnel junction MTJ serving as a resistive element. This voltage change cannot be quickly produced with a large RC (resistance-capacitance) time constant of the sense current path, making it impossible to increase the data read operation speed.
Moreover, as shown in FIG. 86, the data write operation is conducted based on the relation between the applied magnetic field and the asteroid characteristic line provided as a threshold. Accordingly, variation in asteroid characteristic line as produced in manufacturing the memory cells results in variation in data write margin to the memory cell.
FIG. 89 is a conceptual diagram illustrating the effects of the manufacturing variation on the data write margin.
Referring to FIG. 89, the design value of the asteroid characteristic line is denoted with ASd. It is now assumed that the asteroid characteristic line of the memory cell is deviated from the design value, as shown by ASa or ASb.
For example, in the MTJ memory cell having the asteroid characteristic line ASb, the data cannot be written even if the data write current according to the design value is supplied for application of the data write magnetic field.
On the other hand, in the MTJ memory cell having the asteroid characteristic line ASa, the data is written even if the data write magnetic field smaller than the design value is applied. As a result, the MTJ memory cell having such characteristics is extremely susceptible to the magnetic noise.
Such manufacturing variation in asteroid characteristic line may further be increased as the memory cells are miniaturized for improved integration. Accordingly, in order to ensure the manufacturing yield, there is a need not only for development of the manufacturing technology that reduces the manufacturing variation in asteroid characteristic line, but also for the adjustment technology for ensuring an appropriate data write margin corresponding to the variation in asteroid characteristic line.
Moreover, as described in connection with FIGS. 85 and 86, a relatively large data write current must be supplied to the bit line BL and the write word line WWL in the data write operation. As the data write current is increased, the current density in the bit line BL and the write word line WWL is also increased, which may possibly cause a phenomenon called electromigration.
Electromigration may cause disconnection or short-circuit of the wirings, thereby possibly degrading the operation reliability of the MRAM device. Moreover, an increased data write current may possibly produce a considerable amount of magnetic noise. It is therefore desirable to realize the structure capable of writing the data with a smaller data write current.
As described in connection with FIGS. 87 and 88, a large number of wirings are required to write and read the data to and from the MTJ memory cell, making it difficult to reduce the area of the memory array integrating the MTJ memory cells, and thus the chip area of the MRAM device.
An MTJ memory cell using a PN junction diode as an access element instead of the access transistor is known as a memory cell structure capable of achieving improved integration over the MTJ memory cell shown in FIG. 83.
FIG. 90 is a schematic diagram showing the structure of the MTJ memory cell using the diode.
Referring to FIG. 90, the MTJ memory cell using the diode includes a magnetic tunnel junction MTJ and an access diode DM. The access diode DM is coupled between the magnetic tunnel junction MTJ and the word line WL. Herein, the direction from the magnetic tunnel junction MTJ toward the word line WL is the forward direction. The bit line BL extending in such a direction that crosses the word line WL is coupled to the magnetic tunnel junction MTJ.
In the MTJ memory cell using the diode, the data write operation is conducted with the data write current being supplied to the word line WL and the bit line BL. As in the case of the memory cell using the access transistor, the direction of the data write current is set according to the write data level.
On the other hand, in the data read operation, the word line WL corresponding to the selected memory cell is set to the low voltage (e.g., ground voltage Vss) state. By precharging the bit line BL to the high voltage (e.g., power supply voltage Vcc) state, the access diode DM is rendered conductive, allowing the sense current Is to be supplied through the magnetic tunnel junction MTJ. The word lines WL corresponding to the non-selected memory cells are set to the high voltage state. Therefore, the corresponding access diodes DM are retained in the OFF state, and no sense current Is flows therethrough.
Thus, the data read and write operations can be conducted also in the MTJ memory cell using the access diode.
FIG. 91 is a structural diagram of the MTJ memory cell of FIG. 90 provided on the semiconductor substrate.
Referring to FIG. 91, the access diode DM is formed on the semiconductor substrate SUB from an N-type region NWL formed from, e.g., an N-type well, and a P-type region PRA formed thereon.
The N-type well NWL, which corresponds to the cathode of the access diode DM, is coupled to the word line WL provided in the metal wiring layer M1. The P-type region PRA, which corresponds to the anode of the access diode DM, is electrically coupled to the magnetic tunnel junction MTJ through the barrier metal 140 and the metal film 150. The bit line BL is provided in the metal wiring layer M2 so as to be coupled to the magnetic tunnel junction MTJ. Thus, by replacing the access transistor with the access diode, the MTJ memory cell that is advantageous in terms of improvement in integration degree can be obtained.
The data write current flows through the word line WL and the bit line BL in the data write operation. This causes a voltage drop on these lines. Such a voltage drop may turn ON the PN junction of the access diode DM of at least one of the MTJ memory cells that are not selected for the data write operation. As a result, a current may unexpectedly flow through the MTJ memory cell, causing an erroneous data write operation.
Thus, the conventional MTJ memory cell using the access diode is advantageous in terms of improved integration, but is problematic in view of the stability of the data write operation.